The present invention relates to a clamp circuit preferably used for protecting a signal input terminal of a semiconductor integrated circuit device.
For example, a semiconductor integrated circuit device incorporating an A/D converter has input terminals into which analog voltage signals are entered as detection result from various detectors.
FIG. 4 shows a clamp circuit employable for this kind of semiconductor integrated circuit device to prevent an overvoltage (i.e., excessive voltage) exceeding a withstand voltage from entering into this IC device.
A clamp circuit 1 shown in FIG. 4 includes resistors R1 and R2 provided in a signal input path 4 connected to an input terminal of a semiconductor integrated circuit device (i.e., IC) 2 incorporating an A/D converter. A zener diode ZD1 is connected between a joint point of two resistors R1 and R2 and a ground line 5. The zener diode ZD1 has a zener voltage Vz being set to be lower than a withstand voltage of IC 2. When an input voltage exceeds the zener voltage Vz, the zener diode ZD1 clamps the input voltage to the zener voltage Vz.
According to this arrangement, the resistors R1 and R2 and the zener diode ZD1 cooperatively constitute an external clamping hardware set required for each input terminal 3. When IC 2 has a plurality of input terminals 3, it is necessary to provide the same number of external clamping hardware sets. This will require an increased substrate surface area for mounting these external clamping hardware sets and accordingly the fabrication or manufacturing costs will increase.
Furthermore, U.S. Pat. No. 5,479,119 discloses an overvoltage protection circuit capable of protecting a sensitive circuit element (e.g., A/D converter) against saturation and damage when subjected to an excessive voltage. FIG. 5 shows a circuit arrangement of this overvoltage protection circuit. An overvoltage protection circuit 6 shown in FIG. 5 includes an out-of-range detector 7 which compares an input signal with reference levels to determine if it is within a predetermined range of acceptable inputs, a supplemental signal source 8 which generates a supplemental signal within a predetermined range, and a control circuit 10 which supplies the supplemental signal to an A/D converter 9 when the input signal is determined not to be within the predetermined range.
The overvoltage protection circuit 6 shown in FIG. 5 is characterized in that no clamping is applied to an input overvoltage signal and, instead, the input overvoltage signal is substituted by the supplemental signal to be entered into the A/D converter 9, thereby protecting the sensitive circuit element. According to this arrangement, the input overvoltage signal is directly entered into the out-of-range detector 7. This makes it difficult to form the out-of-range detector 7 and the A/D converter 9 on the same chip, when the IC uses CMOS processes or comparable low withstand processes.
In view of the above-described problems of the prior art, the present invention has an object to provide a clamp circuit preferably applicable to a signal input terminal of a semiconductor integrated circuit to reduce the number of external clamping circuit elements required for the clamping circuit.
In order to accomplish the above and other related objects, the present invention provides a clamp circuit including a comparing circuit for comparing a voltage of a signal input terminal with a predetermined clamp voltage and generating a clamp action command signal when the voltage of the signal input terminal exceeds the predetermined clamp voltage. A voltage output circuit, having a predetermined current output property, is provided for generating a voltage within a predetermined range not exceeding the clamp voltage. A switching circuit is connected between the signal input terminal and the voltage output circuit for performing a closing operation in response to the clamp action command signal generated from the comparing circuit. A semiconductor integrated circuit device incorporates or accommodates the comparing circuit, the voltage output circuit, and the switching circuit. A signal input path is provided outside the semiconductor integrated circuit device and is connected to the signal input terminal. A current limiting element is provided in this signal input path.
According to this arrangement, the comparing circuit compares the voltage of the signal input terminal (hereinafter, referred to as terminal voltage) with the predetermined clamp voltage. The switching circuit, connected between the signal input terminal and the voltage output circuit, performs a switching operation based on the clamp action command signal representing the comparison result. Regarding the clamp action at an upper limit side, the switching circuit is switched into an opened condition when the terminal voltage is not larger than the clamp voltage. An input voltage incoming from the outside enters via the current limiting element into the signal input terminal. Then, the input voltage is supplied to an internal circuit accommodated in the semiconductor integrated circuit device. In general, the input impedance of the internal circuit is so high that substantially no voltage error is caused by the current limiting element provided in the signal input path.
On the other hand, when the terminal voltage exceeds the clamp voltage, the switching circuit is switched into a closed condition. Current flows across the current limiting element provided in the signal input path, the signal input terminal of the semiconductor integrated circuit device, and the switching circuit. Then, the current enters into the voltage output circuit. This current causes a voltage drop at the current limiting element. The terminal voltage approaches to an output voltage of the voltage output circuit which is set at a level not exceeding the clamp voltage. When the terminal voltage becomes equal to or smaller than the clamp voltage, the switching circuit turns into the opened condition. In other words, only the limited duration that the incoming signal exceeds the clamp voltage, the comparing circuit controls the switching operation of the switching circuit based on the comparison between the terminal voltage and the clamp voltage so as to clamp the terminal voltage to an upper limit value of the clamp voltage.
Similarly, the above-described explanation is applied to the clamp action at a lower limit side. Namely, when the terminal voltage exceeds the clamp voltage in the negative direction, the switching circuit is switched into the closed condition. Current flows from the voltage output circuit across the switching circuit, the signal input terminal, and the external current limiting element.
Accordingly, the present invention makes it possible to clamp the terminal voltage to a desirable clamp voltage when an incoming signal is an overvoltage input exceeding the clamp voltage. Setting the clamp voltage to an appropriate value within a withstand voltage of the semiconductor integrated circuit device makes it possible to surely protect the semiconductor integrated circuit device against such an overvoltage input. The clamp circuit of the present invention requires only the current limiting element as the external element provided outside the semiconductor integrated circuit device. This is effective to reduce the substrate surface area required for mounting the external clamping circuit elements. The fabrication or manufacturing costs can be reduced.
Preferably, the comparing circuit includes a comparator which operates in response to a predetermined power source voltage supplied from a power source line and has one input terminal connected to the signal input terminal and the other input terminal connected to the power source line. In this comparator, transistors constituting an active load circuit in a differential amplifying circuit have a current output property ratio being set based on a difference between the clamp voltage and the power source voltage.
According to this arrangement, the comparator possesses an offset voltage corresponding to the current output property ratio of the transistors constituting an active load circuit. When one input terminal of the comparator is connected to the signal input terminal and the other input terminal is connected to the power source line, the terminal voltage is compared with a voltage (equivalent to the clamp voltage) being shifted from the power source line voltage by the offset voltage. Accordingly, there is no necessity of providing a clamp voltage generating circuit for generating a clamp voltage. The circuit arrangement can be simplified.
It is also preferable that the comparing circuit, the switching circuit and the current limiting element are provided for each signal input terminal when the semiconductor integrated circuit device has a plurality of signal input terminals, and the voltage output circuit is commonly provided for the plurality of signal input terminals.
According to this arrangement, as the voltage output circuit is commonly used for the plurality of signal input terminals, it becomes possible to reduce overall electric power consumption at the voltage output circuit.
It is also preferable that the comparing circuit, the current limiting element is a resistor.
This is effective to reduce a substrate surface area required for mounting the external clamping circuit elements. The fabrication or manufacturing costs can be reduced.
It is also preferable that the voltage output circuit has a current output property at least equivalent to |Vmxe2x88x92VCL|/Rxc3x97N, where Vm represents a maximum voltage of a signal having not passed the resistor, VCL represents the clamp voltage, R represents a resistance value of the resistor, and N represents the total number of signal input terminals.
According to this arrangement, when the maximum voltage Vm is simultaneously applied to the total of N signal input terminals, the voltage output circuit can supply the current flowing across each switching circuit so as to surely clamp the terminal voltage to the clamp voltage.
It is also preferable that the signal input terminal is an analog signal input terminal connected to an A/D converter provided in the semiconductor integrated circuit device.
According to this arrangement, the terminal voltage is fixed to the clamp voltage when the incoming signal is an overvoltage input exceeding the clamp voltage.